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| products and specifications discussed herein ar e subject to change by micron without notice. 64mb: x4, x8, x16 sdram features pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_1.fm - rev. n 12/08 en 1 ?2000 micron technology, inc. all rights reserved. synchronous dram mt48lc16m4a2 ? 4 meg x 4 x 4 banks mt48lc8m8a2 ? 2 meg x 8 x 4 banks mt48lc4m16a2 ? 1 meg x 16 x 4 banks for the latest data sheet, refer to micron?s web site: www.micron.com/sdram features ? pc100- and pc133-compliant ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operatio n; column address can be changed every clock cycle ? internal banks for hiding row access/precharge ? programmable burst lengths: 1, 2, 4, 8, or full page ? auto precharge, includes concurrent auto precharge and auto refresh modes ? self refresh modes: standard and low power (not available on at devices) ?refresh ? 64ms, 4,096-cycle refresh (15.6s/row) (commercial, industrial) ? 16ms, 4,096-cycle refresh (3.9s/row) (automotive) ? lvttl-compatible inputs and outputs ? single +3.3v 0.3v power supply table 1: address table 16 meg x 4 8 meg x 8 4 meg x 16 configuration 4 meg x 4 x 4 banks 2 meg x 8 x 4 banks 1 meg x 16 x 4 banks refresh count 4k 4k 4k row addressing 4k (a0?a11) 4k (a0?a11) 4k (a0?a11) bank addressing 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) column addressing 1k (a0?a9) 512 (a0?a8) 256 (a0?a7) notes: 1. refer to micron technical note: tn-48-05 . 2. off-center parting line. 3. contact micron for product availability. part number example: mt48lc8m8a2tg-75:g options marking ? configurations ? 16 meg x 4 (4 meg x 4 x 4 banks) ? 8 meg x 8 (2 meg x 8 x 4 banks) ? 4 meg x 16 (1 meg x 16 x 4 banks) 16m4 8m8 4m16 ?write recovery ( t wr) ? t wr = ?2 clk? 1 a2 ?plastic package ? ocpl 2 ? 54-pin tsop ii (400 mil) ? 54-pin tsop ii (400 mil) pb-free, rohs-compliant ? 54-ball vfbga 8mm x 8mm (x16 only) ? 54-ball vfbga 8mm x 8mm, pb-free, rohs-compliant (x16 only) tg p f4 b4 3 ? timing (cycle time) ? 7.5ns @ cl = 3 (pc133) ? 7.5ns @ cl = 2 (pc133) ? 6ns @ cl = 3 (x16 only) -75 -7e -6 ? self refresh ? standard ? low power none l ? operating temperature range ? commercial (0c to +70c) ? industrial (?40c to +85c) ? automotive (?40c to +105c) none it at 3 ?design revision :g
pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_1.fm - rev. n 12/08 en 2 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram general description notes: 1. fbga device decoder: http:/ /www.micron.com/su pport/fbga/fbga.asp general description the micron ? 64mb sdram is a high-speed cm os, dynamic random-access memory containing 67,108,864 bits. it is internally configured as a quad-bank dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the x4?s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits. each of the x8?s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8 bits. each of the x16?s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. read and write accesses to the sdram are bu rst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0?a11 select the row). the address bits registered coincident with the read or write command are used to select the star ting column location for the burst access. the sdram provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca- tions, or the full page, with a burst terminat e option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the 64mb sdram uses an internal pipelined architecture to achieve high-speed opera- tion. this architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, table 2: key timing parameters cl = cas (read) latency speed grade clock frequency access time setup time hold time cl = 2 cl = 3 -6 166 mhz ? 5.5ns 1.5ns 1ns -7e 143 mhz ? 5.4ns 1.5ns 0.8ns -75 133 mhz ? 5.4ns 1.5ns 0.8ns -7e 133 mhz 5.4ns ? 1.5ns 0.8ns -75 100 mhz 6ns ? 1.5ns 0.8ns table 3: 64mb sdram part numbers part numbers architecture package mt48lc16m4a2tg 16 meg x 4 54-pin tsop ii mt48lc16m4a2p 16 meg x 4 54-pin tsop ii mt48lc8m8a2tg 8 meg x 8 54-pin tsop ii mt48lc8m8a2p 8 meg x 8 54-pin tsop ii mt48lc4m16a2tg 4 meg x 16 54-pin tsop ii mt48lc4m16a2p 4 meg x 16 54-pin tsop ii mt48lc4m16a2b4 1 4 meg x 16 54-ball vfbga mt48lc4m16a2f4 1 4 meg x 16 54-ball vfbga pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_1.fm - rev. n 12/08 en 3 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram automotive temperature fully random access. precharging one bank wh ile accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. the 64mb sdram is designed to operate in 3.3v memory systems. an auto refresh mode is provided, along with a power-saving, po wer-down mode. all inputs and outputs are lv t tl -c om pati b le. sdrams offer substantial advances in dr am operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to inte rleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. automotive temperature the automotive temperature (at) option adheres to the following specifications: ? 16ms refresh rate ? self refresh not supported ? ambient and case temperatures cannot be less than ?40c or greater than 105c pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdramtoc.fm - rev. n 12/08 en 4 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 automotive temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 functional block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 pin/ball assignments and descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 mode register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 operating mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 write burst mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 command inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 bank/row activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 clock suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 burst read/single write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 temperature and thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdramlof.fm - rev. n 12/08 en 5 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram list of figures list of figures figure 1: 16 meg x 4 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 2: 8 meg x 8 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 3: 4 meg x 16 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: pin assignment (top view) 54-pin tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 5: ball assignment (top view, ball down) x16, 54-ball vf bga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 6: mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 7: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 8: activating a specific row in a specific bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 9: example: meeting t rcd (min) when 2 < t rcd (min)/ t ck 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 10: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 11: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 12: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 13: random read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 14: read-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 15: read-to-write with extra clock cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 16: read-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 17: terminating a read bu rst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 18: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 19: write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 20: write-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 21: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 22: write-to-read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 23: write-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 24: terminating a write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 25: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 26: power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 27: clock suspend during write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 28: clock suspend during read burs t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 29: read with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 30: read with auto precharge interr upted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 31: write with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 32: write with auto precharge interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 33: example temperature test point location, 54-pin tsop : top view . . . . . . . . . . . . . . . . . . . . . . . . . . .4 6 figure 34: example temperature test point location, 54-ball vfbg a: top view . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 35: initialize and load mode regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 36: power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 37: clock suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 38: auto refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 39: self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 40: read ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 41: read ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 42: single read ? without auto prec harge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 43: single read ? with auto precha rge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 44: alternating bank read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 45: read ? full-page burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 46: read ? dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 47: write ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 48: write ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 49: single write ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 figure 50: single write ? with auto precha rge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 51: alternating write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 52: write ? full-page burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 53: write ? dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 54: 54-pin plastic tsop ii (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 55: 54-ball vfbga ?f4/b4? package, 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdramlot.fm - rev. n 12/08 en 6 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram list of tables list of tables table 1: address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: 64mb sdram part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 4: pin/ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 5: burst definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 6: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 7: truth table 1 ? commands and dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 8: truth table 2 ? cke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 9: truth table 3 ? current state bank n, command to bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 10: truth table 4 ? current state bank n, command to bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 11: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 12: temperature limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 13: thermal impedance simulated values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 14: dc electrical characteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 15: i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 16: tsop capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 17: vfbga capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 18: electrical characteristics and re commended ac operating conditions . . . . . . . . . . . . . . . . . . . . . . .48 table 19: ac functional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 7 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram functional block diagrams functional block diagrams figure 1: 16 meg x 4 sdram 12 ras# cas# row- address mux clk cs# we# cke control logic column- address counter/ latch mode register 10 command decode a0?a11, ba0, ba1 dqm 12 address register 14 1024 (x4) 4096 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (4,096 x 1,024 x 4) bank0 row- address latch & decoder 4096 sense amplifiers bank control logic dq0?dq3 4 4 data input register data output register 4 12 bank1 bank2 bank3 12 10 2 1 1 2 refresh counter pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 8 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram functional block diagrams figure 2: 8 meg x 8 sdram 12 ras# cas# row- address mux clk cs# we# cke control logic column- address counter/ latch mode register 9 command decode a0?a11, ba0, ba1 dqm 12 address register 14 512 (x8) 4096 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (4,096 x 512 x 8) bank0 row- address latch & decoder 4096 sense amplifiers bank control logic dq0?dq7 8 8 data input register data output register 8 12 bank1 bank2 bank3 12 9 2 1 1 2 refresh counter pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 9 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram functional block diagrams figure 3: 4 meg x 16 sdram 12 ras# cas# row- address mux clk cs# we# cke column- address counter/ latch 8 a0?a11, ba0, ba1 dqml, dqmh 12 address register 14 256 (x16) 4096 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (4,096 x 256 x 16) bank0 row- address latch & decoder 4096 sense amplifiers bank control logic dq0?dq15 16 16 data input register data output register 16 12 bank1 bank2 bank3 12 8 2 2 2 2 refresh counter control logic mode register command decode pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 10 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram pin/ball assignments and descriptions pin/ball assignments and descriptions figure 4: pin assignment (top view) 54-pin tsop notes: 1. the # symbol indica tes signal is active low. a dash (-) indicates x8 and x4 pin function is same as x16 pin function. figure 5: ball assignment (top view, ball down) x16, 54-ball vfbga notes: 1. the balls at a4, a5, and a6 are absent from the physical pac kage. they are in cluded to illus- trate that rows 4, 5, and 6 exis t, but contain no solder balls. v dd dq0 v dd q dq1 dq2 vssq dq3 dq4 v dd q dq5 dq6 vssq dq7 v dd dqml we# cas# ras# cs# ba0 ba1 a10 a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 vss dq15 vssq dq14 dq13 v dd q dq12 dq11 vssq dq10 dq9 v dd q dq8 vss nc dqmh clk cke nc a11 a9 a8 a7 a6 a5 a4 vss x8 x16 x16 x8 x4 x4 - dq0 - nc dq1 - nc dq2 - nc dq3 - nc - nc - - - - - - - - - - - - - nc - nc dq0 - nc nc - nc dq1 - nc - nc - - - - - - - - - - - - - dq7 - nc dq6 - nc dq5 - nc dq4 - nc - - dqm - - - - - - - - - - - - nc - nc dq3 - nc nc - nc dq2 - nc - - dqm - - - - - - - - - - - a b c d e f g h j 12345678 v ss dq14 dq12 dq10 dq8 dqmh nc/a12 a8 v ss dq15 dq13 dq11 dq9 nc clk a11 a7 a5 v ss q v dd q v ss q v dd q v ss cke a9 a6 a4 v dd q v ss q v dd q v ss q v dd cas# ba0 a0 a3 dq0 dq2 dq4 dq6 dqml ras# ba1 a1 a2 v dd dq1 dq3 dq5 dq7 we# cs# a10 v dd 9 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 11 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram pin/ball assignments and descriptions table 4: pin/ba ll descriptions tsop pin numbers vfbga ball numbers symbol type description 38 f2 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also incremen ts the internal burst counter and controls the output registers. 37 f3 cke input clock enable: cke activates (high) and deactivates (low) the clk signal. deactivating the clock pr ovides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank), or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power- down and self refresh modes, wher e cke becomes asynchronous until after exiting the same mode. the in put buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cke may be tied high. 19 g9 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all co mmands are masked when cs# is registered high, but read/write bursts alr eady in progress will continue and dqm will retain it s dq mask capability while cs# remains high. cs# provides for exte rnal bank selection on systems with multiple banks. cs# is cons idered part of the command code. 16, 17, 18 f9, f7, f8 we#, cas#, ras# input command inputs: we#, cas#, and ras# (along with cs#) define the command being entered. 39 ? x4, x8: dqm input input/output mask: dqm is an input mask signal for write accesses and an output enable signal for read accesses. inpu t data is masked when dqm is sampled high duri ng a write cycle. the output buffers are placed in a high-z state (two-clo ck latency) when dqm is sampled high during a read cycle. on the x4 and x8, dqml (pin 15) is a nc and dqmh is dqm. on the x16, dqml corresponds to dq0?dq7 and dqmh corresponds to dq8?dq15. dqml and dqmh are considered same state when referenced as dqm. 15, 39 e8, f1 x16: dqml, dqmh 20, 21 g7, g8 ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank the active, read, write or precharge command is being applied. 23?26, 29?34, 22, 35 h7, h8, j8, j7, j3, j2, h3, h2, h1, g3, h9, g2 a0?a11 input address inputs: a0?a11 are sample d during the active command (row-address a0?a11) and read/wr ite command (column-address a0?a9 [x4]; a0?a8 [x8]; a0?a7 [x 16]; with a10 de fining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether all banks are to be precharged (a10[high]) or bank selected by ba0, ba1 (a1[low ]). the address inputs also provide the op-code during a load mode register command. 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 a8, b9, b8, c9, c8, d9, d8, e9, e1, d2, d1, c2, c1, b2, b1, a2 dq0?dq15 x16: i/o data input/output: data bus for x16 (4, 7, 10, 13, 42, 45, 48, and 51 are ncs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are ncs for x4). 2, 5, 8, 11, 44, 47, 50, 53 ? dq0?dq7 x8: i/o data input/output: data bus for x8 (2, 8, 47, 53 are ncs for x4). 5, 11, 44, 50 ? dq0?dq3 x4: i/o data input/output: data bus for x4. 40 e2 nc ? no connect: these pins should be left unconnected. pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 12 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram functional description functional description in general, the 64mb sdram (4 meg x 4 x 4 banks, 2 meg x 8 x 4 banks, and 1 meg x 16 x 4 banks) is a quad-bank dram that operates at 3.3v and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the x4?s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits. each of the x8?s 16,777,216-bit banks is organized as 4,096 ro ws by 512 columns by 8 bits. each of the x16?s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. read and write accesses to the sdram are bu rst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registrati on of an active command which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the ba nk and row to be accessed (ba0 and ba1 select the bank, a0?a11 select the row). the address bits (x4: a0?a9; x8: a0?a8; x16: a0?a7) registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. initialization sdrams must be powered up and initiali zed in a predefined manner. operational procedures other than those specified may resu lt in undefined operation. after power is applied to v dd and v dd q (simultaneously) and the cloc k is stable (stable clock is defined as a signal cycling wi thin timing constraints specified for the clock pin), the sdram requires a 100s delay prior to is suing any command other than a command inhibit or nop. starting at some point during this 100s period and continuing at least through the end of this period, comman d inhibit or nop commands must be applied. once the 100s delay has been satisfied wi th at least one command inhibit or nop command having been applied, a precharge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. after the idle state, at least two auto re fresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register program- ming. because the mode register will power up in an unknown state, it must be loaded prior to applying any operational command. if desired, the two auto refresh commands can be issued after the load mode register command. 36 g1 nc ? no connect: may be used as addr ess inputs (a12) on the 256mb and 512mb devices. 3, 9, 43, 49 a7, b3, c7, d3 v dd q supply dq power: isolated dq power on the die for improved noise immunity. 6, 12, 46, 52 a3, b7, c3, d7 v ss q supply dq ground: isolated dq ground on the die for improved noise immunity. 1, 14, 27 a9, e7, j9 v dd supply power supply: +3.3v 0.3v. 28, 41, 54 a1, e3, j1 v ss supply ground. table 4: pin/ba ll descriptions tsop pin numbers vfbga ball numbers symbol type description pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 13 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram functional description the recommended power-up sequence for sdrams: 1. simultaneously apply power to v dd and v dd q. 2. assert and hold cke at a lvttl logic low since all inputs and outputs are lvttl- compatible. 3. provide stable clock signal. stable clock is defined as a signal cycling within timing constraints specified for the clock pin. 4. wait at least 100s prior to issuing any command other than a command inhibit or nop. 5. starting at some point during this 100s period, bring cke high. continuing at least through the end of this period, 1 or more command inhibit or nop commands must be applied. 6. perform a precharge all command. 7. wait at least t rp time; during this time nops or deselect commands must be given. all banks will complete their precharge, th ereby placing the device in the all banks idle state. 8. issue an auto refresh command. 9. wait at least t rfc time, during which only nops or command inhibit commands are allowed. 10. issue an auto refresh command. 11. wait at least t rfc time, during which only nops or command inhibit commands are allowed. 12. the sdram is now ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded with desired bit values prior to applying any operational command. usin g the load mode register command, program the mode register. the mode register is programmed via the mode regis- ter set command with ba1 = 0, ba0 = 0 and retains the stored information until it is programmed again or the device loses power. not programming the mode register upon initialization will result in default settings which may not be desired. outputs are guaranteed high-z after the load mo de register command is issued. outputs should be high-z already before the load mode register command is issued. 13. wait at least t mrd time, during which only nop or deselect commands are allowed. at this point the dram is ready for any valid command. note: if desired, more than two auto refres h commands can be issued in the sequence. after steps 9 and 10 are complete, repeat them until the desired number of auto refresh + t rfc loops is achieved. register definition mode register the mode register is used to define the spec ific mode of operation of the sdram. this definition includes the selection of a burst length, a burst type, a cl, an operating mode and a write burst mode, as shown in figure 6 on page 15. the mode register is programmed via the load mode register command and will retain the stored infor- mation until it is programmed again or the device loses power. mode register bits m0?m2 specify the burs t length, m3 specifies the type of burst (sequential or interleaved), m4?m6 specify the cl, m7 and m8 specify the operating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use. pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 14 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram functional description the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subs equent operation. violating either of these requirements will result in unspecified operation. burst length read and write accesses to the sdram are bu rst oriented, with the burst length (bl) being programmable, as shown in figure 6 on page 15. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. bl = 1, 2, 4, or 8 locations are avai lable for both the sequential and the inter- leaved burst types, and a full-page burst is available for the sequential mode. the full- page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states cannot be used because unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses fo r that burst take place within this block, meaning that the burst will wrap within the bl ock if a boundary is reached. the block is uniquely selected by a1?a9 (x4), a1?a8 (x8) or a1?a7 (x16) when bl = 2; by a2?a9 (x4), a2?a8 (x8) or a2?a7 (x16) when bl = 4; an d by a3?a9 (x4), a3?a8 (x8) or a3?a7 (x16) when bl = 8. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached. pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 15 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram functional description figure 6: mode register definition burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 5 on page 16. 3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 ? 0 ? defined ? 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas la tency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6?m0 m8 m7 op mode a10 a11 10 11 reserved wb 0 1 write burst mode programmed burst length single location access m9 program ba0, ba1, m11, m10 = ?0, 0? to ensure compatibility with future devices. pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 16 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram functional description notes: 1. for full-page accesses: y = 1,024 (x4); y = 512 (x8); y = 256 (x16). 2. for bl = 2, a1?a9 (x4), a1?a8 (x8), or a1?a7 (x16) select the block-of-two burst; a0 selects the starting column within the block. 3. for bl = 4, a2?a9 (x4), a2?a8 (x8), or a2?a7 (x16) select the block-of-four burst; a0?a1 select the starting column within the block. 4. for bl = 8, a3?a9 (x4), a3?a8 (x8), or a3?a7 (x16) select the block-of-eight burst; a0?a2 select the starting column within the block. 5. for a full-page burst, the full row is selected and 6. a0?a9 (x4), a0?a8 (x8), or a0?a7 (x16) select the starting column. 7. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 8. for bl = 1, a0?a9 (x4), a0?a8 (x8), or a0?a7 (x 16) select the unique column to be accessed, and mode register bit m3 is ignored. cas latency cl is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier ( n + m - 1 ), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access time s are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dqs wi ll start driving after t1 and the data will be valid by t2, as shown in figure 7 on pa ge 17. table 6 on page 17 indicates the oper- ating frequencies at which each cl setting can be used. table 5: burst definition burst length starting column address order of accesses within a burst type = sequential type = interleaved 2a0 00-1 0-1 11-0 1-0 4a1a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2a1a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a0?a9/8/7 (location 0?y) cn, cn + 1, cn + 2 cn + 3, cn + 4... ?cn - 1, cn? not supported pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 17 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram functional description reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 7: cas latency operating mode the normal operating mode is selected by se tting m7 and m8 to zero; the other combi- nations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed vi a m0?m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to re ad bursts, but write accesses are single-locat ion (nonburst) accesses. table 6: cas latency speed allowable operating frequency (mhz) cl = 2 cl = 3 -6 ? 166 -7e 133 143 -75 100 133 clk dq t2 t1 t3 t0 cl = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t3 t0 cl = 2 lz d out t oh t command nop read t ac nop pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 18 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands commands truth table 1 provides a quick reference of available commands. this is followed by a written description of each command. three additional truth tables appear following ?operation? on page 21; these tables provid e current state/next state information. notes: 1. a0?a11 define the op-code written to the mode register. 2. a0?a11 provide row address, and ba0, ba 1 determine which bank is made active. 3. a0?a9 (x4), a0?a8 (x8), or a0?a7 (x16) prov ide column address; a10 (high) enables the auto precharge feature (nonpers istent), while a10 (low) disa bles the auto precharge fea- ture; ba0, ba1 determine which bank is being read from or written to. 4. a10 (low): ba0, ba1 determine the bank being precharged. a10 high: all banks pre- charged and ba0, ba1 are ?don?t care.? 5. this command is auto refresh if cke is (high), self refresh if cke is low. 6. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 7. activates or deactivates the dqs during wri tes (zero-clock delay) and reads (two-clock delay). command inhibit the command inhibit function prevents new commands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effectively dese- lected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram that is selected (cs# is low). this prevents unwant ed commands from being registered during idle or wait states. operations al ready in progress are not affected. table 7: truth table 1 ? commands and dqm operation cke is high for all commands shown except self refresh. name (function) cs# ras# cas# we# dqm addr dqs notes command inhibit (nop) hxxxx x x no operation (nop) l hhhx x x active (select bank and activate row) llhhxbank/rowx 2 read (select bank and colu mn, and start read burst) lhlhl/h8bank/colx 3 write (select bank and column , and start write burst) l h l l l/h8 bank/col valid 3 burst terminate lhhlx x active precharge (deactivate row in bank or banks) llhlxcode x 4 auto refresh or soft refresh (enter self refresh mode) lllhx x x5, 6 load mode register llllxop-codex 1 write enable/output enable ????l ? active7 write inhibit/output high-z ????h ?high-z7 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 19 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands load mode register the mode register is loaded via inputs a0?a11. see mode register heading in ?register definition? on page 13. the load mode register command can only be issued when all banks are idle, and a subsequent exec utable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a9 (x4), a0? a8 (x8), or a0?a7 (x16) selects the starting column location. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. read data appears on the dqs subject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was regis- tered high, the corresponding dqs will be high-z two clocks later; if the dqm signal was registered low, the dqs will provide valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a9 (x4), a0?a8 (x8), or a0?a7 (x16) selects the starti ng column location. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subseq uent accesses. input data appearing on the dqs is written to the memory array subject to the dqm input logic level appearing coin- cident with the data. if a given dqm signal is registered low, the corresponding data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? after a bank has been precharged, it is in the idle state and must be acti- vated prior to any read or write commands being issued to that bank. auto precharge auto precharge is a feature that performs the same individual-bank precharge function described above, without requiring an explic it command. this is accomplished by using a10 to enable auto precharge in conjunctio n with a specific read or write command. pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 20 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands a precharge of the bank/row that is addr essed with the read or write command is automatically performed upon completion of the read or write burst, except in the full-page burst mode, where auto precharge does not apply. auto precharge is nonper- sistent in that it is either enabled or di sabled for each individual read or write command. auto precharge ensures that the precharge is in itiated at the earliest valid stage within a burst. the user must not issue another comma nd to the same bank until the precharge time ( t rp) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as desc ribed for each burst type in ?operation? on page 21. burst terminate the burst terminate command is used to truncate either fixed-length or full-page bursts. the most recently registered read or write command prior to the burst terminate command will be truncated, as sh own in the operation section of this data sheet. the burst terminate command does not precharge the row; the row will remain open until a precharge command is issued. auto refresh auto refresh is used during normal operation of the sdram and is analogous to cas#-before-ras# (cbr) refresh in conventional drams. this command is nonper- sistent, so it must be issued each time a refresh is required. all active banks must be precharged prior to issuing an auto refresh command. the auto refresh command should not be issued until the minimum t rp has been met after the precharge command as shown in the operation section. the addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. regardless of device width, the 64mb sdram requires 4,096 auto refresh cy cles every 64ms (commercial and indus- trial) or 16ms (automotive) . providing a distributed auto refresh command every 15.625s (commercial and industrial) or 3.906 s (automotive) will meet the refresh requirement and ensure that each row is refreshed. alternatively, 4,096 auto refresh commands can be issued in a burst at the minimum cycle rate ( t rfc), once every 64ms (commercial and industrial) or 16ms (automotive). self refresh the self refresh command can be used to reta in data in the sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). after the self refresh co mmand is registered, all the inputs to the sdram become ?don?t care,? with the exception of cke, which must remain low. after self refresh mode is engaged, the sdram provides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indefinite period beyond that. pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 21 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (stable clock is defi ned as a signal cycling within timing constraints specified for the clock pin) prior to cke going back high. after cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr, because time is required for the completion of an y internal refresh in progress. upon exiting the self refresh mode, auto refresh commands must be issued every 15.625s or less, as both self refresh and auto refresh utilize the row refresh counter. self refresh is not supported on automotive temperature devices. operation bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be ?opened.? this is accomplished via the active command, which selects both the bank and the row to be activated (see figure 8). after opening a row (issuing an active co mmand), a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks, rounded to 3. this is reflected in figure 9 on page 22, which covers any case where 2 < t rcd (min)/ t ck 3. (the same procedure is used to convert other specification limits from time units to clock cycles). a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active comma nds to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active co mmands to different banks is defined by t rrd. pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 22 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands figure 8: activating a specific row in a specific bank figure 9: example: meeting t rcd (min) when 2 < t rcd (min)/ t ck 3 reads read bursts are initiated with a read co mmand, as shown in figure 10 on page 23. the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out elem ent from the starting column address will be available following the cl after the read command. each subsequent data-out element will be valid by the next positive clock edge. figure 11 on page 24 shows general timing for each possible cl setting. upon completion of a burst, assuming no other commands have been initiated, the dqs will go high-z. a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) cs# we# cas# ras# cke clk a0?a10, a11 row address don?t care high ba0, ba1 bank address clk t2 t1 t3 t0 t command nop active read or write nop rcd (min) t rcd (min) +0.5 t ck t ck t ck t ck don?t care pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 23 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands data from any read burst may be truncate d with a subsequent read command, and data from a fixed-length read burst may be immediately followed by data from a read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl -1. this is shown in figure 12 on page 25 for cl = 2 and cl = 3; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. the 64mb sdram uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. a read command can be initiated on any clock cycle following a previous read command. full-speed random read accesses can be performed to the same bank, as shown in figure 13 on page 26, or each subsequent read may be performed to a different bank. figure 10: read command cs# we# cas# ras# cke clk column address a0?a9: x4 a0?a8: x8 a0?a7: x16 a10 ba0, ba1 don?t care high enable auto precharge disable auto precharge bank address a11: x4 a9, a11: x8 a8, a9, a11: x16 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 24 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands figure 11: cas latency clk dq t2 t1 t3 t0 cl = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t3 t0 cl = 2 lz d out t oh t command nop read t ac nop pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 25 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands figure 12: consecutive read bursts note: each read command may be to any bank. dqm is low. don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 cycle cas latency = 2 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read nop t7 x = 2 cycles cas latency = 3 transitioning data pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 26 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands figure 13: random read accesses note: each read command may be to any bank. dqm is low. data from any read burst may be truncate d with a subsequent write command, and data from a fixed-length read burst may be immediately followed by data from a write command (subject to bus turnaround limitations). the write burst may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that i/o cont ention can be avoided. in a given system design, there may be a possibility that the device driving the input data will go low-z before the sdram dqs go high-z. in this case, at least a single-cycle delay should occur between the last read data and the write command. the dqm input is used to avoid i/o contention, as shown in figures 14 and 15 on page 27. the dqm signal must be asserted (hig h) at least two clocks prior to the write command (dqm latency is two clocks for output buffers) to suppress data-out from the read. once the write command is registered, the dqs will go high-z (or remain high-z), regardless of the state of the dqm signal, provided the dqm was active on the clock just prior to the write command that truncated the read command. if not, the second write will be an invalid write. fo r example, if dqm was low during t4 in, then the writes at t5 and t7 would be vali d, while the write at t6 would be invalid. clk dq t2 t1 t4 t3 t6 t5 t0 command address read nop nop bank, col n don?t care d out n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop bank, col n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m cas latency = 2 cas latency = 3 transitioning data pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 27 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands the dqm signal must be de-asserted prior to the write command (dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. figure 14 shows the case where the clock frequency allows for bus contention to be avoided without adding a nop cycle, and figure 15 sh ows the case where the additional nop is needed. figure 14: read-to-write note: cl = 3 is used for illustration. the read command may be to any bank, and the write command may be to any bank. if a burst of one is used, then dqm is not required. figure 15: read-to-writ e with extra clock cycle note: cl = 3 is used for illustration. the read command may be to any bank, and the write command may be to any bank. don?t care read nop nop write nop clk t2 t1 t4 t3 t0 dqm dq d out n command d in b address bank, col n bank, col b ds t hz t t ck transitioning data don?t care read nop nop nop nop dqm clk dq d out n t2 t1 t4 t3 t0 command address bank, col n write d in b bank, col b t5 ds t hz t transitioning data pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 28 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands a fixed-length read burst may be followed by, or truncated with, a precharge command to the same bank (provided that au to precharge was not activated), and a full- page burst may be truncated with a precharge command to the same bank. the precharge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl -1. this is shown in figure 16 for each possible cl; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data element(s). in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as desc ribed above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvan- tage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. full-page read bursts can be truncated with the burst terminate command, and fixed-length read bursts may be truncated with a burst terminate command, provided that auto precharge was not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl = -1. this is shown in figure 17 on page 29 for each possible cl; data element n + 3 is the last desired data element of a longer burst. figure 16: read-to-precharge note: dqm is low. clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 precharge nop t7 don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 precharge nop x = 1 cycle cl = 2 cl = 3 x = 2 cycles transitioning data pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 29 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands figure 17: terminating a read burst note: dqm is low. writes write bursts are initiated with a write command, as shown in figure 18 on page 30. the starting column and bank addresses ar e provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at th e completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dqs will remain high-z, and any additional input data will be ignored (see figure 19 on page 30). a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) data for any write burst may be truncate d with a subsequent write command, and data for a fixed-length write burst may be immediately followed by data for a write command. the new write command can be issued on any clock following the previous write command, and the data provided coin cident with the new command applies to the new command. don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 burst terminate active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 burst terminate active t rp t7 x = 1 cycle cl = 2 cl = 3 x = 2 cycles bank a , col n bank a , row bank ( a or all) bank a , col n bank a , row bank ( a or all) transitioning data pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 30 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands an example is shown in figure 20 on page 31. data n + 1 is either the last of a burst of two or the last desired of a longer burst. the 64mb sdram uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. a write command can be initiated on any clock cycle following a previous write command. full-speed random write accesses within a pa ge can be performed to the same bank, as shown in figure 21 on page 32, or each subsequent write may be performed to a different bank. figure 18: write command figure 19: write burst note: note: bl = 2. dqm is low. don?t care valid address cs# we# cas# ras# cke clk column address a10 high enable auto precharge disable auto precharge a0?a9: x4 a0?a8: x8 a0?a7: x16 a11: x4 a9, a11: x8 a8, a9, a11: x16 ba0, ba1 bank address clk dq d in n t2 t1 t3 t0 command address nop nop don?t care write d in n + 1 nop bank, col n transitioning data pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 31 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands figure 20: write-to-write note: dqm is low. each write command may be to any bank. data for any write burst may be truncate d with a subsequent read command, and data for a fixed-length write burst may be immediately followed by a subsequent read command. after the read command is register ed, the data inputs will be ignored, and writes will not be executed. an example is shown in figure 22 on page 32. data n + 1 is either the last of a burst of two or the last desired of a longer burst. data for a fixed-length write burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not acti- vated), and a full-page write burst may be truncated with a precharge command to the same bank. the precharge command should be issued t wr after the clock edge at which the last desired input data element is registered. the auto precharge mode requires a t wr of at least one clock plus time, rega rdless of frequency. in addition, when truncating a write burst, the dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge command. an example is shown in figure 23 on page 33. data n + 1 is either the last of a burst of two or the last desired of a longer burst. foll owing the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as desc ribed above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvan- tage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. clk dq t2 t1 t0 command address nop write write bank, col n bank, col b d in n d in n + 1 d in b don?t care transitioning data pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 32 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands figure 21: random write cycles note: each write command may be to any bank. dqm is low. figure 22: write-to-read note: the write command may be to any bank, and the read command may be to any bank. dqm is low. cl = 2 for illustration. don?t care clk dq d in n t2 t1 t3 t0 command address write bank, col n d in a d in x d in m write write write bank, col a bank, col x bank, col m transitioning data don?t care clk dq t2 t1 t3 t0 command address nop write bank, col n d in n d in n + 1 d out b read nop nop bank, col b nop d out b + 1 t4 t5 transitioning data pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 33 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands figure 23: write-to-precharge note: dqm could remain low in this example if the write burst is a fixed length of two. fixed-length or full-page write bursts can be truncated with the burst terminate command. when truncating a write burst, the input data applied coincident with the burst terminate command will be ignored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate command. this is shown in figure 24 on page 34, where data n is the last desired data element of a longer burst. precharge the precharge command (figure 25 on page 34) is used to deactivate the open row in a particular bank or the open row in all bank s. the bank(s) will be available for a subse- quent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 ar e treated as ?don?t care.? after a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. don?t care dqm clk dq t2 t1 t4 t3 t0 command address bank a , col n t5 nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row dqm dq command address bank a , col n nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row t6 nop nop t wr @ t clk 15ns t wr = t clk < 15ns transitioning data pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 34 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands power-down power-down occurs if cke is registered low coincident with a nop or command inhibit when no accesses are in progress. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and outp ut buffers, excluding cke, for maximum power savings while in standby. the device may not remain in the power-down state longer than the refresh period ( t ref or t ref at ) since no refresh operations are performed in this mode. the power-down state is exited by regi stering a nop or command inhibit and cke high at the desired clock edge (meeting t cks). see figure 26 on page 35. figure 24: terminating a write burst note: dqms are low. figure 25: precharge command don?t care clk dq t2 t1 t0 command address bank, col n write burst terminate next command d in n (address) (data) transitioning data cs# we# cas# ras# cke clk a10 don?t care high all banks bank selected a0?a9 ba0,1 bank address valid address pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 35 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands figure 26: power-down clock suspend the clock suspend mode occurs when a column access/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deactivated, ?freezing? the synchronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the dq pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (see examples in figures 27 and 28 on page 36.) clock suspend mode is exited by registering cke high; the internal clock and related operation will resume on the subsequent positive clock edge. burst read/single write the burst read/single write mode is entere d by programming the write burst mode bit (m9) in the mode register to a logic 1. in this mode, all write commands result in the access of a single column location (burst of one), regardless of the programmed burst length. read commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (m9 = 0). don?t care t ras t rcd t rc all banks idle input buffers gated off exit power-down mode. ( ) ( ) ( ) ( ) ( ) ( ) t cks > t cks command nop active enter power-down mode. nop clk cke ( ) ( ) ( ) ( ) pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 36 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands figure 27: clock suspend during write burst figure 28: clock suspend during read burst note: for this example, cl = 2, bl = 4 or greater, and dqm is low. concurrent auto precharge an access command (read or write) to an other bank while an access command with auto precharge enabled is executing is not allowed by sdrams, unless the sdram supports concurrent auto precharge. mi cron sdrams support concurrent auto precharge. four cases where concurrent auto precharge occurs are defined below. don?t care d in command address write bank, col n d in n nop nop clk t2 t1 t4 t3 t5 t0 cke internal clock nop d in n + 1 d in n + 2 transitioning data don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 cke internal clock nop transitioning data pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 37 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands read with auto precharge ? interrupted by a read (with or without auto precharge): a read to bank m will inter- rupt a read on bank n , cl later. the precharge to bank n will begin when the read to bank m is registered (figure 29 on page 37). ? interrupted by a write (with or with out auto precharge): a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 30 on page 38). write with auto precharge ? interrupted by a read (with or without auto precharge): a read to bank m will inter- rupt a write on bank n when registered, with the data -out appearing cl later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (figure 31 on page 38). ? interrupted by a write (with or with out auto precharge): a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m (figure 32 on page 39). figure 29: read with auto precharge interrupted by a read note: dqm is low. don?t care clk dq d out a t2 t1 t4 t3 t6 t5 t0 command read - ap bank n nop nop nop nop d out a + 1 d out d d out d + 1 nop t7 bank n cas latency = 3 (bank m ) bank m address idle nop bank n , col a bank m , col d read - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active read with burst of 4 precharge rp - bank n t rp - bank m cas latency = 3 (bank n ) transitioning data pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 38 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands figure 30: read with auto precharge interrupted by a write notes: 1. dqm is high at t2 to prevent d out a +1 from contending with d in d at t4. figure 31: write with auto precharge interrupted by a read notes: 1. dqm is low. clk dq d out a t2 t1 t4 t3 t6 t5 t0 command nop nop nop nop d in d + 1 d in d d in d + 2 d in d + 3 nop t7 bank n bank m address idle nop dqm bank n , col a bank m , col d write - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active write with burst of 4 write-back rp - bank n t wr - bank m cas latency = 3 (bank n ) read - ap bank n 1 don?t care transitioning data don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in a + 1 d in a nop nop t7 bank n bank m address bank n , col a bank m , col d read - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active read with burst of 4 t t rp - bank m d out d d out d + 1 cas latency = 3 (bank m ) rp - bank n wr - bank n transitioning data pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 39 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands figure 32: write with auto pr echarge interrupted by a write notes: 1. dqm is low. notes: 1. cke n is the logic state of cke at clock edge n ; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the sd ram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of command n . 4. all states and sequences not sh own are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that t cks is met). 6. exiting self refresh at clock edge n will put the device in the all banks idle state after t xsr is met. command inhibit or nop co mmands should be issued on any clock edges occurring during the t xsr period. a minimum of two nop commands must be provided during t xsr period. 7. after exiting clock suspend at clock edge n , the device will resume operation and recognize the next command at clock edge n + 1 . table 8: truth table 2 ? cke notes 1?4 apply to entire table cke n-1 cke n current state command n action n notes l l power-down x maintain power-down self refresh x maintain self refresh clock suspend x mainta in clock suspend l h power-down command inhibit or nop e xit power-down 5 self refresh command inhibit or nop exit self refresh 6 clock suspend x exit clock suspend 7 h l all banks idle command inhi bit or nop power-down entry all banks idle auto refresh self refresh entry reading or writing write or nop clock suspend entry h h see table 9 on page 40 don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in d + 1 d in d d in a + 1 d in a + 2 d in a d in d + 2 d in d + 3 nop t7 bank n bank m address nop bank n , col a bank m , col d write - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active write with burst of 4 write-back wr - bank n t rp - bank n t wr - bank m transitioning data pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 40 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands notes: 1. this table applies when cke n-1 was high and cke n is high (see table 8 on page 39) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted; i.e., the current state is for a specific bank, and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: 4. the following states must not be interrupted by a command issued to the same bank. com- mand inhibit or nop commands or allowabl e commands to the other bank should be issued on any clock edge occurring during th ese states. allowable commands to the other bank are determined by its current state and table 9 and according to table 10 on page 42. 5. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on each positive cl ock edge during these states. table 9: truth table 3 ? current state bank n , command to bank n (notes 1?6 apply to entire table; no tes appear below and on next page) current state cs# ras# cas# we# command (action) notes any hxxx command inhibit (nop/continue previous operation) l hhh no operation (nop/continue previous operation) idle l l h h active (select and activate row) lllh auto refresh 7 llll load mode register 7 llhl precharge 11 row activelhlh read (select column and start read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (deactivate row in bank or banks) 8 read (auto precharge disabled) lhlh read (select column and start new read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (truncate read burst, start precharge) 8 lhhl burst terminate 9 write (auto precharge disabled) lhlh read (select column and start read burst) 10 lhl l write (select column an d start new write burst) 10 llhl precharge (truncate write burst, start precharge) 8 lhhl burst terminate 9 idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regist er accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, wi th auto precharge disabled, and has not yet terminated or been terminated. precharging: starts with registration of a pr echarge command and ends when t rp is met. after t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. after t rcd is met, the bank will be in the row active state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a writ e command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. refreshing: starts with registration of an aut o refresh command and ends when t rc is met. after t rc is met, the sdram will be in the all banks idle state. pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 41 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands 6. all states and sequences not sh own are illegal or reserved. 7. not bank-specific; require s that all banks are idle. 8. may or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. not bank-specific; burst terminate affects th e most recent read or write burst, regard- less of bank. 10. reads or writes listed in the command (act ion) column include reads or writes with auto precharge enabled and reads or wr ites with auto precharge disabled. 11. does not affect the state of the ba nk and acts as a nop to that bank. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. after t mrd is met, the sdram will be in the all banks idle state. precharging all: starts with registration of a prec harge all command and ends when t rp is met. after t rp is met, all banks wi ll be in the idle state. pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 42 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands notes: 1. this table applies when cke n-1 was high and cke n is high (see table 8 on page 39) and after t xsr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given comma nd is allowable). exceptions are covered in the notes below. 3. current state definitions: 4. auto refresh, self refresh, and load mo de register commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. table 10: truth table 4 ? current state bank n , command to bank m (notes 1?6 apply to entire table; no tes appear below and on next page) current state cs# ras# cas# we# command (action) notes any hxxx command inhibit (nop/continue previous operation) l hhh no operation (nop/continue previous operation) idle xxxx any command otherwise allowed to bank m row activating, active, or precharging llhh active (select and activate row) lhlh read (select column and start read burst) 7 lhl l write (select column and start write burst) 7 llhl precharge read (auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start new read burst) 7, 10 lhl l write (select column and start write burst) 7, 11 llhl precharge 9 write (auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 12 lhl l write (select column an d start new write burst) 7, 13 llhl precharge 9 read (with auto precharge) llhh active (select and activate row) lhlh read (select column and start new read burst) 7, 8, 14 lhl l write (select column and start write burst) 7, 8, 15 llhl precharge 9 write (with auto precharge) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 8, 16 lhl l write (select column an d start new write burst) 7, 8, 17 llhl precharge 9 idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regi ster accesses are in progress. read: a read burst has been initiated, wi th auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled, and ends when t rp has been met. after t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a writ e command with auto precharge enabled, and ends when t rp has been met. after t rp is met, the bank will be in the idle state. pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 43 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram commands 6. all states and sequences not sh own are illegal or reserved. 7. reads or writes to bank m listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. concurrent auto precharge: bank n will initiate the auto precharge command when its burst has been interrupted by bank m ?s burst. 9. burst in bank n continues as initiated. 10. for a read without auto precharge interrup ted by a read (with or without auto pre- charge), the read to bank m will interrupt the read on bank n , cl later (figure 12 on page 25). 11. for a read without auto precharge interrup ted by a write (with or without auto pre- charge), the write to bank m will interrupt the read on bank n when registered (figures 14 and 15 on page 27). dqm should be used one clock prior to the write com- mand to prevent bus contention. 12. for a write without auto precharge interru pted by a read (with or without auto pre- charge), the read to bank m will interrupt the write on bank n when registered (figure 22 on page 32), with the data-out appearing cl later. the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 13. for a write without auto precharge interrupt ed by a write (with or without auto pre- charge), the write to bank m will interrupt the write on bank n when registered (figure 20 on page 31). the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 14. for a read with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n , cl later. the precharge to bank n will begin when the read to bank m is registered (figure 29 on page 37). 15. for a read with auto precharge interrupted by a write (with or with out auto precharge), the write to bank m will interrupt the read on bank n when registered . dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 30 on page 38). 16. for a write with auto precha rge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cl later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in regis- tered one clock prior to the read to bank m (figure 31 on page 38). 17. for a write with auto precha rge interrupted by a write (wit h or without auto precharge), the write to bank m will interrupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is regis- tered. the last valid write to bank n will be data registered one clock prior to the write to bank m (figure 32 on page 39). pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 44 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram electrical specifications electrical specifications stresses greater than those listed in table 11 may cause permanent damage to the device. this is a stress rating only, and functi onal operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to abso lute maximum rating conditio ns for extended periods may affect reliability. temperature and thermal impedance it is imperative that the sdram device?s temperature specifications, shown in figure 12 on page 45, be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specifications. an important step in maintaining the proper junction temperature is using the device?s thermal impedances correctly. the thermal impedances are listed in table 13 on page 45 for the applicable die revision and pack- ages being made available. these thermal impedance values vary according to the density, package, and particular design used for each device. incorrectly using thermal impedances can produce significant errors. read micron tech- nical note, tn-00-08, ?thermal applications ,? prior to using the thermal impedances listed in table 13. to ensure the compatibil ity of current and future designs, contact micron applications engineering to confirm thermal impedance values. the sdram device?s safe junction temperature range can be maintained when the tc specification is not exceeded. in applications where the device's ambient temperature is too high, use of forced air and/or heat sinks may be required to satisfy the case tempera- ture specifications. table 11: absolute maximum ratings parameter min max units voltage on v dd , v dd q supply relative to v ss ?1v +4.6 v voltage on inputs, nc or i/o pins relative to v ss ?1v +4.6 v operating temperature t a (commercial) t a (industrial) t a (automotive) 0 ?40 ?40 70 +85 +105 c storage temperature (plastic) ?55 +150 c power dissipation ?1w pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 45 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram electrical specifications notes: 1. max operating case temperature, t c , is measured in the center of the package on the top side of the device, as shown in figure 33 and figure 34 on page 46. 2. device functionality is not guarant eed if the device exceeds maximum t c during operation. 3. all temperature specific ations must be satisfied. 4. the case temperature should be measured by gluing a thermocouple to the top center of the component. this shou ld be done with a 1mm bead of conductive epoxy, as defined by the jedec eia/jesd51 standards. care should be taken to ensure the thermocouple bead is touching the case. 5. operating ambient temperatur e surrounding the package. notes: 1. for designs expected to last beyond the die revision listed, contact micron applications engineering to confirm thermal impedance values. 2. thermal resistance data is sampled from mult iple lots, and the values should be viewed as typical. 3. these are estimates; actual results may vary. ta bl e 1 2 : te mp er a t ure l im it s parameter symbol min max units notes operating case temperature: commercial industrial automotive t c 0 ?40 ?40 80 90 105 c 1, 2, 3, 4 junction temperature: commercial industrial automotive t j 0 ?40 ?40 85 95 110 c 3 ambient temperature: commercial industrial automotive t a 0 -40 -40 70 85 105 c 3, 5 peak reflow temperature t peak ?260c table 13: thermal impedance simulated values die revision package substrate ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) g 54-pin tsop 4-layer 70.5 61.2 57.2 54.6 13.7 54-ball vfbga 2-layer 80.6 67.7 61.5 46.1 4.9 4-layer 64 57.1 53.5 45.7 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 46 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram electrical specifications figure 33: example temperature test point location, 54-pin tsop: top view figure 34: example temperature test point location, 54-ball vfbga: top view 22.22mm 11.11mm test point 10.1 6 mm 5.08mm 8.00mm 4.00mm test point 4.00mm 8.00mm pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 47 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram electrical specifications table 14: dc electrical characteristics and operating conditions notes 1, 5, 6 apply to entire table; notes appe ar on pages 50 and 51; v dd , v dd q = +3.3v 0.3v parameter/condition symbol min max units notes supply voltage v dd , v dd q3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 22 input low voltage: logic 0; all inputs v il ?0.3 0.8 v 22 input leakage current: any input 0v v in v dd (all other pins not under test = 0v) i i ?5 5 a output leakage current: dqs are disabled; 0v v out v dd q i oz ?5 5 a output levels: output high volt age (iout = ?4ma) output low voltage (iout = 4ma) v oh 2.4 ? v v ol ?0.4v table 15: i dd specifications and conditions notes 1, 5, 6 apply to entire table; notes appe ar on pages 50 and 51; v dd , v dd q = +3.3v 0.3v parameter/condition symbol max units notes -6 -7e -75 operating current: active mode; burst = 2; read or write; t rc t rc (min) i dd 1 150 125 115 ma 3, 18, 19, 32 standby current: power-down mode; all banks idle; cke = low i dd 2222ma 32 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd 3 60 45 45 ma 3, 12, 19, 32 operating current: burst mode; page burst; read or write; all banks active i dd 4 180 150 140 ma 3, 18, 19, 32 auto refresh current: cke = high; cs# = high t rfc = t rfc (min) i dd 5 250 230 210 ma 3, 12, 18, 19, 32, 33 t rfc = 15.625s i dd 6333 t rfc = 3.906s (at) i dd 6666 self refresh current: cke 0.2v standard i dd 7111ma 4 low power (l) 0.5 0.5 0.5 table 16: tsop capacitance note 2 applies to entire table; notes appear on pages 50 and 51 parameter symbol min max units notes input capacitance: clk c i 12.53.5 pf 29 input capacitance: all other input-only pins c i 22.53.8 pf 30 input/output capacitance: dqs c io 4.0 6.0 pf 31 table 17: vfbga capacitance note 2 applies to entire table; notes appear on pages 50 and 51 parameter symbol min max units notes input capacitance: clk c i 1tbdtbd pf 29 input capacitance: all other input-only pins c i 2tbdtbd pf 30 input/output capacitance: dqs c io tbd tbd pf 31 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 48 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram electrical specifications table 18: electrical characteristics and recommended ac operating conditions notes 5, 6, 8, 9, 11, 34 ap ply to entire table; notes appear on pages 50 and 51; v dd , v dd q = +3.3v 0.3v ac characteristics symbol -6 -7e -75 units notes parameter min max min max min max access time from clk (positive edge) cl = 3 t ac(3) ? 5.5 ? 5.4 5.4 ns 27 cl = 2 t ac(2)???5.4?6ns address hold time t ah 1 ? 0.8 ? 0.8 ? ns address setup time t as 1.5 ? 1.5 ? 1.5 ? ns clk high-level width t ch 2.5 ? 2.5 ? 2.5 ? ns clk low-level width t cl 2.5 ? 2.5 ? 2.5 ? ns clock cycle time cl = 3 t ck(3) 6 ? 7 ? 7.5 ? ns 23 cl = 2 t ck(2) ? ? 7.5 ? 10 ? ns 23 cke hold time t ckh1 ?0.8?0.8? ns cke setup time t cks 1.5 ? 1.5 ? 1.5 ? ns cs#, ras#, cas#, we#, dqm hold time t cmh1 ?0.8?0.8? ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 ? 1.5 ? 1.5 ? ns data-in hold time t dh 1 ? 0.8 ? 0.8 ? ns data-in setup time t ds 1.5 ? 1.5 ? 1.5 ? ns data-out high-z time cl = 3 t hz(3) ? 5.5 ? 5.4 ? 5.4 ns 10 cl = 2 t hz(2) ? ? ? 5.4 ? 6 ns 10 data-out low-z time t lz1?1?1? ns data-out hold time (load) t oh2?3?3? ns data-out hold time (no load) t ohn 1.8 ? 1.8 ? 1.8 ? ns 28 active-to-precharge command t ras 42 120,000 37 120,000 44 120,000 ns active-to-active command period t rc 60 ? 60 ? 66 ? ns active-to-read or write delay t rcd18?15?20? ns refresh period (4,096 rows) t ref ? 64 ? 64 ? 64 ms refresh period?automotive (4,096 rows) t ref at ?16?16?16ms auto refresh period t rfc60?66?66? ns precharge command period t rp 18 ? 15 ? 20 ? ns active bank a to active bank b command t rrd12?14?15? ns transition time t t 0.3 1.2 0.3 1.2 0.3 1.2 ns 7 write recovery time t wr 1 clk + 6ns ?1 clk + 7ns ?1 clk + 7.5ns ??24 12 ? 14 ? 15 ? ns 25 exit self refresh-to-active command t xsr70?67?75? ns 20 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 49 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram electrical specifications table 19: ac functional characteristics notes 5, 6, 8, 9, 11, 34 ap ply to entire table; notes appear on pages 50 and 51; v dd , v dd q = +3.3v 0.3v parameter symbol -6 -7e -75 units notes read/write command to read/write command t ccd111 t ck 17 cke to clock disable or power-down entry mode t cked111 t ck 14 cke to clock enable or power-down exit setup mode t ped 1 1 1 t ck 14 dqm to input data delay t dqd000 t ck 17 dqm to data mask during writes t dqm000 t ck 17 dqm to data high-z during reads t dqz222 t ck 17 write command to input data delay t dwd000 t ck 17 data-in to active command t dal 5 4 5 t ck 15, 21 data-in to precharge command t dpl222 t ck 16, 21 last data-in to burst stop command tbdl111 t ck 17 last data-in to ne w read/write command t cdl111 t ck 17 last data-in to precharge command t rdl222 t ck 16, 21 load mode register command to active or refresh command t mrd222 t ck 26 data-out to high-z from precharge command cl = 3 t roh(3)333 t ck 17 cl = 2 t roh(2) ? 2 2 t ck 17 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 50 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram notes notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd , v dd q = +3.3v; f = 1 mhz, t a = 25c; pin under test biased at 1.4v. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0c t a +70c (commercial), ?40c t a +85c (industrial), and ?40c t a +105c (automotive) is ensured. 6. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be pow- ered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh require- ment is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specification, the cl ock and cke must tran- sit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5 v with equivalent load: 10. t hz defines the time at which the output achi eves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. c timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1 ns, then the timing is ref- erenced at v il (max) and v ih (min) and no longer at the 1.5v crossover point. clk should always be 1.5v referenced to crossover. refer to micron technical note tn-48-09 . 12. other input signals are allowed to transiti on no more than once every two clocks and are otherwise at valid v ih or v il levels. 13. i dd specifications are tested after th e device is properly initialized. 14. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 18. the i dd current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. address transitions average on e transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 7.5ns for -75 and -7e, t ck = 6ns for -6. q 50pf pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 51 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram notes 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one-third of the cycle rate. v il undershoot: v il (min) = ?2v for a pulse width 3ns. 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for th e clock pin) during access or precharge states (read, write, including t wr, and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget ( t rp) begins 6ns/7ns/7.5ns/ 7ns after the first clock delay, af ter the last write is executed. 25. precharge mode only. 26. jedec and pc100 specify three clocks. 27. t ac for -75/-7e at cl = 3 with no load is 4.6ns and is guaranteed by design. 28. parameter guaranteed by design. 29. pc100 specifies a maximum of 4pf. 30. pc100 specifies a maximum of 5pf. 31. pc100 specifies a maximum of 6.5pf. 32. for -75, cl = 3 and t ck = 7.5ns; for -7e, cl = 2 and t ck = 7.5ns; for -6, cl = 3 and t ck = 6ns. 33. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 34. the -6 speed grade does not support cl = 2. pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 52 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams timing diagrams figure 35: initialize and load mode register notes: 1. if cs# is high at clock high time, all commands applied are nop. 2. the mode register may be loaded prio r to the auto refresh cycles if desired. 3. jedec and pc100 specify three clocks. 4. outputs are guaranteed high -z after command is issued. t ch t cl t ck cke clk command dq ba0, ba1 bank t rfc t mrd t rfc auto refresh auto refresh program mode register 2, 3, 4 t cmh t cms precharge all banks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) t cks power-up: v dd and clk stable t = 100s min precharge nop auto refresh nop load mode register active nop nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) auto refresh all banks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) high-z t ckh ( ) ( ) ( ) ( ) dqm / dqml, dqmh ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) t cmh t cms t cmh t cms a0?a9, a11 row t ah t as code ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a10 row t ah t as code ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) all banks single bank ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) don?t care t0 t1 tn + 1 to + 1 tp + 1 tp + 2 tp + 3 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 53 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 36: power-down mode notes: 1. violating refresh requirements during power-down may result in a loss of data. t ch t cl t ck two clock cycles cke clk dq all banks idle, enter power-down mode precharge all active banks input buffers gated off while in power-down mode exit power-down mode ( ) ( ) ( ) ( ) don?t care t cks t cks command t cmh t cms precharge nop nop active nop ( ) ( ) ( ) ( ) all banks idle ba0, ba1 bank bank(s) ( ) ( ) ( ) ( ) high-z t ah t as t ckh t cks dqm / dqml, dqmh ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a0?a9, a11 row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 tn + 2 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 54 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 37: clock suspend mode notes: 1. for this example, bl = 2, cl = 3, and auto precharge is disabled. 2. x16: a8, a9 and a11 = ?don?t care? x8: a9 and a11 = ?don?t care? x4: a11 = ?don?t care? t ch t cl t ck ac t lz dqm / dqml, dqmh clk a0?a9, a11 dq ba0, ba1 a10 t oh d out m t ah t as t ah t as t ah t as bank t dh d in e t ac t hz d out m + 1 command t cmh t cms nop nop nop nop nop read write don?t care undefined cke t cks t ckh bank column m t ds d in e + 1 nop t ckh t cks t cmh t cms 2 column e 2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 55 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 38: auto refresh mode notes: 1. each auto refresh command performs a re fresh cycle. back-to-back commands are not required. t c h t c l t c k c ke c lk dq t rf c 1 ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) ( ) ( ) c ommand t c mh t c m s nop nop ( ) ( ) ( ) ( ) bank a c tive auto refre s h ( ) ( ) ( ) ( ) nop nop pre c har g e pre c har g e all a c tive b anks auto refre s h t rf c 1 hi g h-z ba0, ba1 bank( s ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ah t a s t c kh t c k s ( ) ( ) nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqm / dqml, dqmh a0?a9, a11 row ( ) ( ) ( ) ( ) all bank s s in g le bank a10 row ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 to + 1 don ? t c are ( ) ( ) ( ) ( ) pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 56 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 39: self refresh mode notes: 1. no maximum time li mit for self refresh mode. t ras(max) applies to non-self refresh mode. 2. t xsr requires minimum of two clocks regardless of frequency and timing. 3. self refresh mode not supported on automotive temperature (at) devices. t ch t cl t ck t rp cke clk dq enter self refresh mode precharge all active banks t xsr 2 clk stable prior to exiting self refresh mode exit self refresh mode (restart refresh time base) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) don?t care command t cmh t cms auto refresh precharge nop nop or command inhibit ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ba0, ba1 bank(s) ( ) ( ) ( ) ( ) high-z t cks ah as auto refresh t ras(min) 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ckh t cks dqm/ dqml, dqmh ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t t a0?a9, a11 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) all banks single bank a10 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 to + 1 to + 2 ( ) ( ) ( ) ( ) pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 57 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 40: read ? without auto precharge notes: 1. for this example, bl = 4, cl = 2, and the read burst is fo llowed by a ?manual? precharge. 2. x16: a8, a9 and a11 = ?don?t care? x8: a9 and a11 = ?don?t care? x4: a11 = ?don?t care? all banks t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t oh d out m +3 t ac t oh t ac t oh t ac d out m +2 d out m +1 t cmh t cms precharge nop nop nop active nop read nop active disable auto precharge single banks don?t care undefined column m 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 dqm / dqml, dqmh cke clk a0?a9, a11 dq ba0, ba1 a10 command pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 58 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 41: read ? with auto precharge notes: 1. for this example, bl = 4, and cl = 2. 2. x16: a8, a9 and a11 = ?don?t care? x8: a9 and a11 = ?don?t care? x4: a11 = ?don?t care? enable auto precharge t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc dqm / dqml, dqmh cke clk a0?a9, a11 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop nop active nop read nop active nop t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 don?t care undefined pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 59 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 42: single read ? without auto precharge notes: 1. for this example, bl = 1, cl = 2, and the read burst is fo llowed by a ?manual? precharge. 2. x16: a8, a9 and a11 = ?don?t care? x8: a9 and a11 = ?don?t care? x4: a11 = ?don?t care? 3. precharge comman d not allowed or t ras would be violated. all banks t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t cmh t cms nop nop 3 nop precharge active nop read active nop disable auto precharge single banks column m 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 dqm / dqml, dqmh cke clk a0?a9, a11 dq ba0, ba1 a10 command don?t care undefined pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 60 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 43: single read ? with auto precharge notes: 1. for this example, bl = 1, and cl = 2. 2. read command not allowed or t ras would be violated. 3. x16: a8, a9 and a11 = ?don?t care? x8: a9 and a11 = ?don?t care? x4: a11 = ?don?t care? enable auto precharge t ch t cl t ck t rp t ras t rcd cas latency t rc dqm / dqml, dqmu cke clk a0?a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank t hz t oh d out m t ac command t cmh t cms nop 2 read active nop nop 2 active nop t ckh t cks column m 3 t0 t1 t2 t4 t3 t5 t6 t7 t8 nop nop don?t care undefined pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 61 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 44: alternating bank read accesses notes: 1. for this example, bl = 4, and cl = 2. 2. x16: a8, a9 and a11 = ?don?t care? x8: a9 and a11 = ?don?t care? x4: a11 = ?don?t care? enable auto precharge t ch t cl t ck t ac t lz dqm / dqml, dqmh clk a0?a9, a11 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row row row t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop active nop read nop active t oh d out b t ac t ac read enable auto precharge row active row bank 0 bank 0 bank 3 bank 3 bank 0 cke t ckh t cks column m 2 column b 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 cas latency - bank 0 t rcd - bank 3 cas latency - bank 3 t t rc - bank 0 rrd don?t care undefined pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 62 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 45: read ? full-page burst notes: 1. for this example, cl = 2. 2. x16: a8, a9 and a11 = ?don?t care? x8: a9 and a11 = ?don?t care? x4: a11 = ?don?t care? 3. page left open; no t rp. t ch t cl t ck t ac t lz t rcd cas latency dqm / dqml, dqmh cke clk a0?a9, a11 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ac t oh d out m +1 row row t hz t ac t oh d out m +1 t ac t oh d out m +2 t ac t oh d out m -1 t ac t oh d out m full-page burst does not self-terminate. can use burst terminate command. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed 3 256 (x16) locations within same row 512 (x8) locations within same row 1,024 (x4) locations within same row command t cmh t cms nop nop nop active nop read nop burst term nop nop ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) t ah t as bank ( ) ( ) ( ) ( ) bank t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) column m 2 t0 t1 t2 t4 t3 t5 t6 tn + 1 tn + 2 tn + 3 tn + 4 don?t care undefined pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 63 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 46: read ? dqm operation notes: 1. for this example, bl = 4, and cl = 2. 2. x16: a8, a9 and a11 = ?don?t care? x8: a9 and a11 = ?don?t care? x4: a11 = ?don?t care? t ch t cl t ck t rcd cas latency dqm / dqml, dqmh cke clk a0-a9, a11 dq ba0, ba1 a10 t cms row bank row bank t ac lz d out m t oh d out m + 3 d out m + 2 t t hz lz t t cmh command nop nop nop active nop read nop nop nop t hz t ac t oh t ac t oh t ah t as t cms t cmh t ah t as t ah t as t ckh t cks enable auto precharge disable auto precharge column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 don?t care undefined pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 64 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 47: write ? without auto precharge notes: 1. for this example, bl = 4, and the wri te burst is followed by a ?manual? precharge. 2. 15ns is required between pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 65 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 48: write ? with auto precharge notes: 1. for this example, bl = 4. 2. x16: a8, a9 and a11 = ?don?t care? x8: a9 and a11 = ?don?t care? x4: a11 = ?don?t care? enable auto precharge t ch t cl t ck t rp t ras t rcd t rc dqm / dqml, dqmh cke clk a0?a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank row row bank t wr d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write nop active t ah t as t ah t as t dh t ds t dh t ds t dh t ds t ckh t cks nop nop column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 don?t care pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 66 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 49: single write ? without auto precharge notes: 1. for this example, bl = 1, and the wri te burst is followed by a ?manual? precharge. 2. 15ns is required between pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 67 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 50: single write ? with auto precharge notes: 1. for this example, bl = 1. 2. x16: a8, a9 and a11 = ?don?t care? x8: a9 and a11 = ?don?t care? x4: a11 = ?don?t care? 3. write command not allowed or t ras would be violated. enable auto precharge t ch t cl t ck t rp t ras t rcd t rc dqm / dqml, dqmh cke clk a0?a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank row row bank t wr d in m command t cmh t cms nop 3 nop 3 nop active nop 3 write nop active t ah t as t ah t as t dh t ds t ckh t cks nop nop column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 don?t care pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 68 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 51: alternating write accesses notes: 1. for this example, bl = 4. 2. x16: a8, a9 and a11 = ?don?t care? x8: a9 and a11 = ?don?t care? x4: a11 = ?don?t care? don?t care t ch t cl t ck clk dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop active nop write nop nop active t dh t ds t dh t ds t dh t ds active write d in b t dh t ds d in b + 1 d in b + 3 t dh t ds t dh t ds enable auto precharge dqm / dqml, dqmh a0?a9, a11 ba0, ba1 a10 t cmh t cms t ah t as t ah t as t ah t as row row row row enable auto precharge row row bank 0 bank 0 bank 1 bank 0 bank 1 cke t ckh t cks d in b + 2 t dh t ds column b 2 column m 2 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t t rcd - bank 0 t wr - bank 0 wr - bank 1 t rcd - bank 1 t t rc - bank 0 rrd t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 69 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 52: write ? full-page burst notes: 1. x16: a8, a9 and a11 = ?don?t care? x8: a9 and a11 = ?don?t care? x4: a11 = ?don?t care? 2. t wr must be satisfied pr ior to prechar ge command. 3. page left open; no t rp. t ch t cl t ck t rcd dqm / dqml, dqmh cke clk a0?a9, a11 ba0, ba1 a10 t cms t ah t as t ah t as row row full-page burst does not self-terminate. can use burst terminate command to stop. 2, 3 ( ) ( ) ( ) ( ) full page completed command t cmh t cms nop nop nop active nop write burst term nop nop ( ) ( ) ( ) ( ) dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 t dh t ds t dh t ds t dh t ds d in m - 1 t dh t ds t dh t ds t ah t as bank ( ) ( ) ( ) ( ) bank t cmh t ckh t cks ( ) ( ) ( ) ( ) 256 (x16) locations within same row 512 (x8) locations within same row 1,024 (x4) locations within same row column m 1 t0 t1 t2 t3 t4 t5 tn + 1 tn + 2 tn + 3 don?t care ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 70 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram timing diagrams figure 53: write ? dqm operation notes: 1. for this example, bl = 4. 2. x16: a8, a9 and a11 = ?don?t care? x8: a9 and a11 = ?don?t care? x4: a11 = ?don?t care? don?t care t ch t cl t ck t rcd dqm / dqml, dqmh cke clk a0?a9, a11 dq ba0, ba1 a10 t cms t ah t as row bank row bank enable auto precharge d in m + 3 t dh t ds d in m d in m + 2 t cmh command nop nop nop active nop write nop nop t cms t cmh t dh t ds t dh t ds t ah t as t ah t as disable auto precharge t ckh t cks column m 2 t0 t1 t2 t3 t4 t5 t6 t7 pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 71 ?2000 micron technology, inc. all rights reserved. 64mb: x4, x8, x16 sdram package dimensions package dimensions figure 54: 54-pin plastic tsop ii (400 mil) notes: 1. all dimensions are in millimeters. 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. see detail a 0.10 +0.10 -0.05 0.15 +0.03 -0.02 2x r 1.00 2x r 0.75 0.80 typ (for reference only) 2x 0.71 0.50 0.10 pin #1 id detail a 22.22 .08 10.16 0.08 11.76 0.20 0.375 0.075 typ 1.2 max 0.25 0.80 2x 0.10 2.80 gage plane plated lead finish: 90% sn, 10% pb or 100%sn plastic package material: epoxy novolac package width and length do not include mold protrusion. allowable protrusion is 0.25 per side. 0.10 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified ov er the power supply and temperat ure range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometime s occur. 64mb: x4, x8, x16 sdram package dimensions pdf: 09005aef80725c0b/source: 09005aef806fc13c micron technology, inc., reserves the right to change products or specifications without notice. 64msdram_2.fm - rev. n 12/08 en 72 ?2000 micron technology, inc. all rights reserved. figure 55: 54-ball vfbga ?f4/b4? package, 8mm x 8mm notes: 1. all dimensions in millimeters. 2. recommended pad = ? 0.40mm smd. ball a1 id 0.65 0.05 seating plane 0.10 c c 1.00 max ball a9 0.80 typ 0.80 typ 3.20 6.40 8.00 0.10 4.00 0.05 solder ball diameter refers to post reflow condition. the pre- reflow diameter is 0.42. 54x ?0.45 0.05 solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn, 3% ag, 0.5% cu solder mask defined ball pads: ?0.40 mold compound: epoxy novolac substrate material: plastic laminate 6.40 3.20 4.00 0.05 8.00 0.10 c l c l ball a1 id ball a1 |
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